1. Field of the Invention
The present invention relates generally to non-volatile semiconductor memory devices, and more particularly, to an electrically erasable and programmable non-volatile semiconductor memory device employing a so-called floating gate-type transistor as a memory cell.
2. Description of the Background Art
FIG. 1A is a diagram including a circuit diagram of four memory cells in a memory cell array and its writing voltage application requirements of a conventional non-volatile semiconductor memory device described in "1988 Symposium on VLSI Circuits, Digest of Technical Papers" pp 81-82. FIG. 1B is a sectional view of a memory cell employed in the non-volatile semiconductor memory device of FIG. 1A. Since in this memory cell, a selecting transistor and a memory transistor are integrated as a single device, a control gate extends in the direction of a source so as to serve as a selecting transistor. In addition, since two transistors are integrated as a single device, a writing blocking voltage needs to be applied in programming.
In FIG. 1A, memory cells 1, 2, 3 and 4 are arranged in matrix in the direction of rows and columns, and constitute a memory cell array. Bit lines are provided in each column of the memory cell array, and word lines are provided in each row. In FIG. 1A, a bit line 5 is provided in a column of the memory cells 1 and 3, and a bit line 6 is provided in a column of the memory cells 2 and 4. Respective drains of the memory cells 1 and 3 are connected to the bit line 5, and respective drains of the memory cells 2 and 4 are connected to the bit line 6. A word line 7 is provided in a row of the memory cells 1 and 2, and a word line 8 is provided in a column of the memory cells 3 and 4. The word line 7 is connected to respective control gates of the memory cells 1 and 2, and the word line 8 is connected to respective control gates of the memory cells 3 and 4. Each source of the memory cells 1-4 is connected to a source line 9. The requirements of application of writing voltage shown in FIG. 1A are for a case where the memory cells 1-4 are erased (writing of "1"), and the memory cell 2 is programmed (writing of "0").
As shown in FIG. 1B, each of the memory cells 1-4 shown in FIG. 1A comprises a control gate 10, a floating gate 11, a drain 12, a source 13, a semiconductor substrate 14, a tunnel oxide film 15, a drain electrode 16, a control gate electrode 17 and a source electrode 18. As described above, the drain electrode 16 is connected to the bit line 5 or 6, the control gate electrode 17 is connected to the word line 7 or 8, and the source electrode 18 is connected to the source line 9.
Now, operation of a conventional non-volatile semiconductor memory device shown in FIG. 1A will be described. In general, in a non-volatile semiconductor memory device there are three fundamental operations of erasing, programming and reading.
First, an erasing operation will be described. In the conventional circuit of FIG. 1A, erasing operation is done for the entire chip. More specifically, all the memory cells included in one chip non-volatile semiconductor memory device are collectively erased, wherein a high-voltage V.sub.PP is applied to all the word lines 7 and 8 in the chip, and 0 V is applied to all the bit lines 5 and 6, to hold the source line 9 in floating state. Since in this state, the high voltage V.sub.PP is applied between each drain 12 of the memory cells 1, 2, 3 and 4, and each control gate 10, high electric field is formed in the tunnel oxide film 15 between the drains 12 and the floating gate 11. Due to the high electric field, electron tunnels from the drain 12 to the floating gate 11 through the tunnel films to be stored in the floating gates 11. As a result, threshold voltages of all the memory cells 1, 2, 3 and 4 with respect to the control gates 10 become higher ("1" is written) compared with those before erasing.
Now, programming operation will be described. In the conventional circuit of FIG. 1A, programming operation is made on a page basis (on a word line basis). Description will be given of an example in which the word line 7 is selected so that "0" is written in the memory cell 2 connected thereto, and other memory cells 1, 3 and 4 do not change. Voltage of 0 V is applied to the selected word line 7, and a writing blocking voltage V.sub.INH is applied to the non-selected word line 8, and a writing blocking voltage V.sub.INH is applied to the bit line 5 and the high voltage V.sub.PP is applied to the bit line 6, to hold the source line 9 held in floating gate state. Since in this state, the high voltage V.sub.PP is applied between the control gate 10 and the drain 12 of the memory cell 2, high electric field is generated between the floating gate 11 and the drain 12. Due to the high electric field, electron tunnels from the floating gate 11 to the drain 12 through the tunnel oxide film 15, so that the floating gate 11 is brought into a depletion state of electrons. Therefore, a threshold voltage of the memory cell 2 with respect to the control gate becomes lower than that before programming ("0" is written). In addition, although voltages of (V.sub.INH -0 V) and (V.sub.PP -V.sub.INH) are applied between the control gate 10 and the drain 12 of the memory cells 1 and 4, respectively, fluctuation of threshold voltage is negligible, since they are sufficiently smaller than the high voltage V.sub.PP in the memory cell 2. In the memory cell 3, as the writing blocking voltages V.sub.INH are applied to both the control gate 10 and the drain 12, potentials are not different, so that threshold voltages do not fluctuate. More specifically, the states of the memory cells 1, 3 and 4 do not change.
Next, the reading operation will be described. Reading is performed by detecting, by means of a sense amplifier (not shown) connected to a bit line, whether current flows from a drain to a source of a memory cell. "0" corresponds to a current flow, and "1" corresponds to no current flow. Now, reading operation of information written in the memory cell 2 will be described. A voltage approximate to a power supply voltage is applied to the selected word line 7, voltage of 0 V is applied to the non-selected word line 8, a reading voltage approximate to 1-2 V is applied to the bit line 6, a voltage of 0 V applied to the bit line 5, and a voltage of 0 V is applied to the source line 9. When "0" is written into the memory cell 2 (when a threshold voltage of a memory cell is low), channels are formed under the floating gate 11, and channels are formed also under the control gate 10 due to the voltage of the selected word line 7 so that, if a reading voltage is applied to the bit line 6, a current flows from the drain 12 to the source 13. When "1" is written in the memory cell 2 (a threshold voltage of a memory cell is high), no channel is formed under the floating gate 11, so that no current flows even if channels are formed under the control gate by the voltage of the selected word line 7.
As described in the foregoing, in a conventional non-volatile semiconductor memory device, erasing is lumped together for chip, and thereafter, programming is made on a page basis. For example, in the case of a memory cell array having 512 word lines, since programming is made on a page (word line) basis after total erasing is made for 512 word lines, writing of non-selected memory cells should be prevented at the maximum of 512 times. That is, the conditions of the memory cell 4 of FIG. 1A, (V.sub.PP -V.sub.INH) is applied 511 times, and the condition of the memory cell 1, (V.sub.INH -0 V) is applied once.
A potential difference between a drain and a control gate of a non-selected memory cell transistor during programming is shown in the following table.
______________________________________ ##STR1## ##STR2## ##STR3## ______________________________________ Transistor 1 ##STR4## ##STR5## ##STR6## Transistor 3 0 V 0 V 0 V Transistor 4 ##STR7## ##STR8## ##STR9## ______________________________________
In the table, when the writing blocking voltage V.sub.INH is, for example, (1/2)V.sub.PP, potential differences between drains and control gates of the transistors 1, 3 and 4 are (1/2V)V.sub.PP, 0 V and (1/2)V.sub.PP, respectively. When the writing blocking voltage V.sub.INH is (1/3)V.sub.PP, potential differences between the drains and the control gates of the transistors 1, 3 and 4 are (1/3)V.sub.PP, 0 V and (2/3)V.sub.PP, respectively.
As described in the foregoing, a conventional non-volatile semiconductor memory device has many word lines and erasing can only be done together on a chip basis, preventing of writing into non-selected memory cells needs to be performed as many times as the number of word lines. Consequently, the margin for fluctuation of voltage when writing is prevented is extremely small. More specifically, since information in non-selected memory cells is destroyed if a voltage for preventing writing fluctuates even one of all the preventing operations of writing into non-selecting memory cells, voltage value for preventing writing needed to be defined very precisely.
FIG. 2 is a graph showing a relation between the number of operations of preventing writing into a transistor of a non-selected memory cell and a threshold voltage Vth of the transistor during programming. As shown in the graph, as the number of operations of preventing writing is increased, the threshold voltage Vth drops, and logic of information stored in the memory cell transistor is inverted from "1" to "0" over a certain number of operations. A critical number of operations depends on a potential difference applied between a drain and a control gate of the memory transistor, that is, the critical number of operations is reduced as the potential difference is increased. In order to prevent destruction of the stored information of non-selected memory cell, the number of operations of preventing writing into the non-selected memory cell should be held below this critical number of operations. In other words, if the number of operations of preventing writing is n2, a potential difference between the drain and the control gate has a margin of (1/2)V.sub.PP to 0 V.